Founding Principal Design Engineer
Gemstar Staffing Group is looking for a Founding Principal Design Engineer for an onsite position located in Palo Alto, CA.
Please send us your resume on our contact us page if you meet the skills below.
Location: Palo Alto, CA
Onsite: 5 days/week
FTE Salary Range: $180,000-$300,000
The Client: The client is building AI agents that automate semiconductor design flows. They just raised $4.5M pre-seed to solve the biggest bottleneck in chip design using AI.
What we're looking for: We need someone with 5+ years of hardware design experience who has led hardware development initiatives at cutting-edge chip companies. You should be comfortable working in high-velocity startup environments and have a track record of building complex hardware systems from scratch. Bonus points if you have strong Python programming skills and experience bridging hardware/software domains.
What you'll do:
Lead RTL, DV, or PD efforts that directly impact our AI-driven chip design platform
Take ownership of hardware evaluation frameworks and drive benchmarking initiatives
Work closely with ML engineers to translate hardware requirements into actionable specifications
Build and maintain hardware testing infrastructure that validates our AI-generated designs
Lead client conversations to understand hardware requirements and translate them for the technical team
Architect and implement hardware evaluation pipelines from requirements gathering to validation
Qualifications:
10+ years of experience. Architecture as a back ground with considerable design experience (multiple products)
Familiarity with standard protocols including I/O ( PCIe, CXL, UCI), standard interface protocols (AXI, etc..), Coherency/CPU protocols
Experienced in writing architectural models in SystemC, ability to translate product concepts into modular algorithmic flows
Design and verification experience in implementing and converging complex SoCs.
2+ years of experience in chip design workflows, ideally contributing to real-world tapeouts at leading chip companies.
Completed 2+ silicon cycles at complex SOC companies
Led complex IP design from spec to silicon
Executed RTL design and synthesis
Exposure to AI-for-chip-design initiatives or a strong understanding of modern ML workflows.
Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related discipline
Expertise in SystemVerilog, Verilog & SoC design methodologies.
Proficiency in Python/Bash for software development.
CPU/processor architecture knowledge
Experience with hardware/software integration
Excellent written and verbal skills - ability to be precise, concise and translate that to junior engineers for implementation.