Founding Principal Verification Engineer- Palo Alto, CA
Gemstar Staffing Group is looking for a Principal Verification Engineer for an hybrid position located in Palo Alto, CA.
Please send us your resume on our contact us page if you meet the skills below.
Founding Principal Verification Engineer- Palo Alto, CA
We’re looking for highly experienced hardware engineers with hands-on expertise in chip design workflows and real-world tapeouts. Ideal candidates will have contributed to silicon at companies like Apple, NVIDIA, Intel, AMD, Etched, or leading EDA vendors. Experience with AI-for-chip-design initiatives or ML-driven design workflows is a strong plus.
Responsibilities
Partner with the Head of Hardware to validate IP and SoCs in-house (e.g., RISC-V, PCIe/CXL, standard I/O, NoC protocols) based on client needs.
Independently define, drive, and coordinate validation, verification, and integration flows, including checkpoints and collateral for multiple IPs.
Collaborate with architecture/design leads and AI/ML experts to generate simulation- and emulation-ready collateral.
Set up and run emulation (Zebu, Palladium) for fast, robust proof-of-concept validation.
Provide domain-specific expertise to ML teams, including architectural/microarchitectural checks, validation modularity, checkers, coverage, and interfaces.
Seamlessly integrate Architect’s products into customer pipelines across RTL, validation, and architecture.
Track emerging trends in semiconductor design and AI-driven design automation to ensure our products remain cutting-edge in quality, scalability, and performance.
Build internal benchmarks and datasets to rigorously evaluate system performance across RTL, validation, and architectural contexts.
Qualifications
Bachelor’s, Master’s, or PhD in Electrical/Computer Engineering or related field.
5+ years (10+ preferred) in semiconductor or EDA environments
Deep expertise in validation, emulation, and architectural/system-level verification of industry-standard IPs, with end-to-end silicon delivery experience a strong plus.
Strong coding skills in SystemVerilog, UVM, and C/C++ for test environments; scripting (Python, Bash) for automation.
Hands-on experience with simulation and emulation flows/methodologies.
Proven track record defining microarchitectural checkers/monitors, modeling IP/SoC validation platforms, and developing modular validation collateral for reuse and scalability.
Experience mapping IP/SoC designs to FPGA prototypes for fast functional verification.
Excellent problem-solving, collaboration, and communication skills, with an eye for detail.
Ability to lead the Design Validation (DV) function over time.
Preferred Experience
Exposure to AI-for-chip-design initiatives
Knowledge of DFT, power optimization, or high-speed/low-power design flows.
IP verification experience with PCIe, CXL, NoC, CPU subsystems, memory controllers, PHY, LPDDR, or similar.